circuit note cn - 0294 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more information and/or support, visit www.analog.com/cn0294. devices connected/referenced adf4351 fractional - n pll synthesizer with integrated vco ADCLK948 clock fanout buffer with 8 lvpecl outputs increasing the n umbe r of o utputs from a c lock s o urce using low jitter lvpecl fanout buffers rev. 0 circuits from the lab? circuits from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and appl icability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuits from the lab circu its. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog device s, inc. all rights reserved. evaluation and desig n support circuit evaluation boards adf4351 evaluation board ( eval - adf435 1 eb1z ) ad clk948 evaluation board ( ADCLK948 / pcbz ) design and integration files schematics, layout files, bill of materials circuit function and benefit s many systems require low jitter multiple system clocks for mixed signal processing and timing. th e circuit shown in figure 1 interface s the adf4351 integrated phase - locked loop ( pll ) and volt age - controlled oscillator ( vco ) to the ADCLK948 , which provides up to eight differential , low voltage , positive emitter coupled logic (lvpecl ) outputs from one differential output of the adf4351 . 22nf 10nf 330nf 180 ? 82 ? spi-compatible serial bus adf4351 v vco v vco v dd 3.3v cp gnd agnd d gnd rf out b? rf out b+ cp out 1nf 1nf 4.7k ? r set le data clk ref in fref in v tune dv dd av dd ce 10 28 16 29 1 2 3 22 8 31 9 11 18 21 27 51 ? a gndvco 14 15 17 20 7 pdb rf 26 sd gnd 6 32 sdv dd v p 5 sw 4 rf out a? rf out a+ 13 12 v vco z bias z bias 1f q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 q5 q5 q6 q6 q7 q7 v t 0 v ref 0 v ref 1 in_sel clk0 clk0 v t 1 clk1 clk1 lvpecl ADCLK948 reference reference 3.3v 3.3v 100 ? 100 ? 100 ? 100 ? 1nf 1nf 3.3v 10989-001 figure 1. adf4351 pll c onnected to ADCLK948 fanout buffer (simplified schematic: all connections an d decoupling not shown)
cn- 0294 circuit not e rev. 0 | page 2 of 5 m ode rn digital systems often require many high quality clocks at logic levels that are different from the logic level of the clock source. e xtra buffering may be required to guarantee accurate distribution to other circuit compo nents without loss of integrity. t he interface between the adf4351 clock source ADCLK948 clock fa n out buffer is described , and measurements show that the additive jitter associated with the clock fanout buffer is 75 fs rms. circuit description the adf4351 is a wideband pll and vco consisting of three separate multi band vcos. each vco covers a range of approximately 700 m hz (with some overlap between the frequencies of the vco ). this permits a fundamental vco frequency range of between 2.2 ghz to 4.4 ghz. f requencies lower than 2.2 ghz can be generated using internal dividers within the adf4351 . f or clock generation , the adf435 1 pll and vco must be enabled , and the desired output frequency must be program med . the output frequency of the a df 435 1 is available at the open - collector outputs at the rf out pins, which require a shunt inductor (or resistor), plus a dc blocking capacitor . the ADCLK948 is a sige low jitter clock fanout buffer that is ideally suited for use with the adf4351 , because its maximum input frequency (4.5 ghz) is just above that of the adf4351 (4.4 ghz). broadband rms additive jitter is 75 fs. it is necessary to add a dc common - mode bias level of 1. 6 5 v to the clk input s of the ADCLK948 to mimic lvpecl logic levels . this is accomplished by the use of a resistor bias network. omission of t he dc bias circuit results in degraded signal integrity at the ADCLK948 outputs. common variation s other possible synthesizers with integrated vcos are the adf43 50 fractional n (137 mhz to 4400 mhz) and the adf4360 integer n series. other possible clock fanout buffers in the same family as the ADCLK948 are the adclk946 (6 lvpecl outputs), adclk950 (10 lvpecl outputs), and the adclk954 (12 lvpecl outputs). circuit e valuation and t est th e circuit is evaluated us ing the eval - adf435 1 eb1z board for a clock source , with some minor modifications . the eval - adf435 1 eb1z board uses the standard adf4351 programming software contained on the cd that accompanies the evaluation board. the ADCLK948 / pcbz is also required and can be used out of the box without modificat ion. equipment needed the following equipment is needed: ? the e va l - adf435 1 eb1z evaluation board kit with programming software ? the ADCLK948pcbz evaluation board ? a 3.3 v power supply ? two cables to connect the 3.3 v supply to the ADCLK948pcbz ? two short equal length sma coaxial cables ? a h igh speed oscilloscope (2 ghz bandwidth) or an equivalent ? the r&s fsup26 spectrum an alyzer or an equivalent ? a pc with windows? xp, windows, vista (32 - bit), or windows 7 (32 - bit) the sma coaxial cable is required to connect the rf out a + and rf out a ? pins of the e va l - adf435 1 eb1z to clk0 and clk0 pins of the ADCLK948pcbz . functional block diagram for this experiment, the ADCLK948pcbz and the e va l - adf435 1 eb1z are used. the boards are connected via a sma cable to the ADCLK948pcbz , as shown in figure 1 . high-speed oscilloscope r&s rto1024 power supply rfouta+ 5 ) 2 8 7 $ pc usb com 3.3v adf4351 evaluation board (eval-adf4351eb1z) t7 ADCLK948/pcbz evaluation board j4 j2 clk0 clk0 out2 out2 10989-002 figure 2. adf4351 logic level measurement setup getting started the ug - 435 user guide details the installation and use of the e va l - adf435 1 eb1z evaluation softwa re. ug - 435 also contains board setup instructions and the board schematic, layout, and bill of materials. necessary modifications to the board are the insertion of 100 ? resistors after the dc blocking capacitor . the resistors are connected to 3.3 v and to gnd. this should be done to both the rf out a + and rf out a? pins to provide a common - mode voltage of 1.65 v (above the minimum required 1.5 v). this may necessitate scrap ing off the solder mask near these transmission lines. the ug - 068 user guide contains similar information relevant to the operation of the ADCLK948 / pcbz evaluation b oard
circuit note cn- 0294 rev. 0 | page 3 of 5 logic level measurement in this example , the rohde & schwarz rto1024 oscilloscope is used together with two rt - zs30 active probes to accurately measure the high speed logic levels . install the adf435x s oftware to pc by doing the following: 1. connect the e va l - adf4351eb1z to the pc, follow the hardware driver instructions as per ug - 435. 2. program the adf4351 pll as p er the screenshot of the adf435x software ( see figure 3 ). in th is example , an rf frequency of 1 ghz is chosen . 3. using two equal length short sma cables , connect the rf out a+ and rf out a? sma connectors from the e va l - adf4351eb1z board to the clk0/ clk0 sma connectors of the ADCLK948 / pcbz board. 4. connect the differential output o ut2/ out2 of the ADCLK948 / pcbz to the high speed oscilloscope. see figure 4 for typical waveforms for a 1 g hz output . 10989-003 figure 3. adf4351 software settings 10989-004 figure 4. ADCLK948 oscilloscope output for 1 ghz logic signal , horizontal axis: 200 ps/ div , vertical axis: 200 mv/ div
cn- 0294 circuit not e rev. 0 | page 4 of 5 phase noise and jitter measurement 1. repeat s tep 1 to step 4 from the logic level measurement section . 2. terminate the unused clk2 output of the ADCLK948/pcbz with a 50 ? load ( s ee figure 5 ) . 3. connect the clk2 output via a sma cable to the signal source analyze r ( s ee figure 5 ) . 4. measure the jitter performance of the signal. figure 6 shows the pha se noise at the output of the adf4351 , and the rms jitter is 32 5.7 fs. figure 7 shows the phase noise at the ADCLK948 output. the rms jit ter is 330 .4 fs. t he additive jitter of the ADCLK948 can be calculated as (330.4 2 ? 325.7 2 ) = 55.5 fs rms . the specified value from the ADCLK948 data sheet is 75 fs rms. spectrum analyzer (r&s fsup26) power supply 50? term rfouta+ rfouta? pc usb com 3.3v adf4351 evaluation board (eval-adf4351eb1z) t7 ADCLK948/pcbz evaluation board j4 j2 clk0 out2 clk0 out2 10989-005 figure 5. adf4351 phase noise and jitter measurement setup r&s fsup 26 signal source analyzer locked settings residual noise [t1 w/o spurs] phase detector +20 db signal frequency: 999.999524 mhz int phn (1.0 k .. 30.0 m) ?56.8 dbc signal level: ?3.86 dbm residual pm 0.117 cross corr mode harmonic 1 residual fm 2.939 khz internal ref tuned internal phase det rms jitter 0.3257 ps phase noise [dbc/hz] marker 1 [t1] marker 2 [t1] marker 3 [t1] marker 4 [t1] rf atten 5 db 1 khz 10 khz 100 khz 1 mhz top ?70 dbc/hz ?101.53 dbc/hz ?104.91 dbc/hz ?113.11 dbc/hz ?142.41 dbc/hz ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 10khz 100khz 1mhz 10mhz 1khz 30mhz ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 spur power (dbc) loopbw 300hz 2 clrwr a 1 clrwr smth 1% spr off th 0db frequency offset 1 2 3 4 10989-006 figure 6. adf4351 output phase noise measurement showing 32 5.7 fs rms jitter
circuit note cn- 0294 rev. 0 | page 5 of 5 r&s fsup 26 signal source analyzer locked settings residual noise [t1 w/o spurs] phase detector +20 db signal frequency: 999.999516 mhz int phn (1.0 k .. 30.0 m) ?56.7 dbc signal level: ?3.86 dbm residual pm 0.119 cross corr mode harmonic 1 residual fm 4.091 khz internal ref tuned internal phase det rms jitter 0.3304 ps phase noise [dbc/hz] marker 1 [t1] marker 2 [t1] marker 3 [t1] marker 4 [t1] rf atten 5 db 1 khz 10 khz 100 khz 1 mhz top ?80 dbc/hz ?101.38 dbc/hz ?104.99 dbc/hz ?113.61 dbc/hz ?142.17 dbc/hz ?16 0 ?15 0 ?14 0 ?13 0 ?12 0 ?11 0 ?10 0 ?9 0 10khz 100khz 1mhz 10mhz 1khz 30mhz ?16 0 ?15 0 ?14 0 ?13 0 ?12 0 ?11 0 ?10 0 ?9 0 spur power (dbc) loopbw 300hz 1 clrwr smth 1% 2 clrwr a spr off th 0db frequency offset 1 2 3 4 10989-007 figure 7. ad clk948 output phase noise measurement showing 3 30 .4 fs rms jitter l earn more cn0232 design support package: http://www.analog.c om/cn0232 - designsupport ug - 435 user guide for the e va l - adf4350eb1z board ug - 068 , user guide for the ADCLK948/ pcbz board mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd , analog devices. mt - 086 tutorial, fundamentals of phase locked loops (plls), analog devices. mt - 101 tutorial, decoupling techniques , analog devices. adisimpll design tool data sheets and evaluation boards adf4351 evaluation board ( eva l - adf435 1 eb1z ) ADCLK948 evaluation board ( ADCLK948 / pcbz ) adf4351 data sheet ADCLK948 data sheet revision history 9 / 1 2 revision 0 : initial version (continued from first page) circuits from the lab circuits are intended only for use with analog devices products and are the intellectual pr operty of analog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or other wise under any patents or other intellectual property by application or use of the circuits from the lab circuits. information furnished by analog devices is believed to be accurate and reliable. however, circuits from the lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other right s of third parties that m ay result from their use. analog devices reserves the right to change any circuits from the lab circuits at any time without notice but is under no obligation to do s o. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn10989 - 0 - 9/12(0)
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